1. Field of the Invention
The present invention relates to a display driving device used in a display apparatus and the like which necessitates a driving LSI referred to as a driver for driving the display such as a liquid crystal display device, an EL display device, and the like. The present invention also relates to a data transmission method used in the display driving device.
2. Description of the Related Art
In the conventional data transmission method used in a display driving device, a method in which image data is transmitted to a driver in the form of digital signals is used.
FIG. 9 shows a schematic diagram of data and a synchronization clock (a sampling clock) which is synchronized with the data in a conventional display driving device. To the display driving device, image data is applied in such a manner that data related to respective one of red (R), green (G), and blue (B) is represented by 8 bits. Herein, the present invention is not directly concerned with a scanning driver (a gate driver), other control signals, and a power supply, so that they are omitted in the description and the drawings.
In FIG. 9, an electronic computer 1 outputs display data such as image data of red (R), green (G), and blue (B) and a synchronization clock. The image data related to respective one of red (R), green (G), and blue (B) is represented by 8 bits. The electronic computer 1 is connected to a control circuit 3. The control circuit 3 performs the control so as to sort the display data into two sets of display data for upper and lower sections of a display screen of a liquid crystal display device 2. The control circuit 3 is connected to an upper-side driver 5 provided on an upper-side driver substrate 4 and a lower-side driver 7 provided on a lower-side driver substrate 6 via transmission line sets 8 and 9, respectively. The upper-side driver 5 and the lower-side driver 7 are connected to the display device 2.
With the above-described construction, the image data of red (R), green (G), and blue (B) each in 8 bits fed to the control circuit 3 together with the synchronization clock from the electronic computer 1 is sorted into two sets of data for the upper-side driver 5 and the lower-side driver 7 by the control circuit 3. The two sets of data are transmitted to the upper-side driver 5 and the lower-side driver 7 via the transmission line sets 8 and 9, respectively. Specifically, in each of the transmission line sets 8 and 9 from the control circuit 3 to the drivers 5 and 7, a line is provided per bit. For example, in a driving circuit using 8-bit data for each of R, G, and B, it is necessary to provide 24 lines only for the image data of red (R), green (G), and blue (B). It is appreciated that, in the cases where a driver is installed on either of the upper side or the lower side, the signal sorting by the control circuit 3 is not performed.
FIG. 10 shows transmission timings of a synchronization clock CK and image data AR, AG, and AB which are transmitted from the control circuit 3 to the upper-side driver 5 in FIG. 9. The transmission timings to the lower-side driver 7 are shown in the same way as in the case of the upper-side driver 5, so that the following description is made only for the upper-side driver 5.
In FIG. 10, numbers attached after the image data AR, AG, and AB indicate the transmission sequence of image data for each color transmitted to the upper-side driver 5. For example, AR1 designates the first transmitted data of red, and AR2 designates the second transmitted data of red. The respective image data AR, AG, and AB are sequentially fed for respective periodic rising edge of the synchronization clock CK.
FIG. 11 shows the connections of the transmission line set 8 provided between the control circuit 3 and the driver 5 in FIG. 9. In the actual driving section, the transmission line set 8 includes a plurality of parts such as line portions on a control circuit board, connectors, electric wires, and line portions on the driver substrate 4. In FIG. 11, the plurality of the parts are collectively shown. In general, it is necessary to use a plurality of drivers 5, and the transmission line set 8 is connected to input terminals (R.sub.0 -R.sub.7, G.sub.0 -G.sub.7, and B.sub.0 -B.sub.7) of each of the plurality of drivers 5. FIG. 11 shows the connection of line set 8 only for one of such drivers 5. For the 8-bit image data AR (input terminals R.sub.0 -R.sub.7), AG (input terminals G.sub.0 -G.sub.7), and AB (input terminals B.sub.0 -B.sub.7) of red (R), green (G), and blue (B), a line is provided per bit. Accordingly, 25 lines in total are required for the image data and the synchronization clock CK.
FIG. 12 shows circuitry of a data input portion of the driver 5 shown in FIG. 9. In FIG. 12, input terminals TR.sub.0 -TR.sub.7, TG.sub.0 -TG.sub.7, and TB.sub.0 -TB.sub.7. Into which the 8-bit image data AR (input terminals R.sub.0 -R.sub.7), AG (input terminals G.sub.0 -G.sub.7), and AB (input terminals B.sub.0 -B.sub.7) of red (R), green (G), and blue (B) are input are respectively connected to input terminals D.sub.0 -D.sub.7 of latch circuits 12 such as D-type flip-flops for respective colors via an input buffer 11. Output terminals Q.sub.0 -Q.sub.7 of these latch circuits 12 are connected to internal bus IR for red, internal bus IG for green, and internal bus IB for blue, respectively. Input terminal TCK to which the synchronization clock CK is input is connected to a line for internal synchronization clock ICK via the input buffer 11, and the line for the internal synchronization clock ICK is connected to clock input terminals of the latch circuits 12 via an inverter 13.
The image data AR (input terminals R.sub.0 -R.sub.7), AG (input terminals G.sub.0 -G.sub.7), and AB (input terminals B.sub.0 -B.sub.7) which are transmitted through the 24 data lines are data-latched by the latch circuits 12 for respective colors in accordance with the inverted synchronization clock which is obtained via the inverter 13. After the phases are matched with the transmission timings again, the image data are transmitted to desired portions in the driver 5. FIG. 13 shows the timings of the internal synchronization clock ICK and the internal image data IR, IG, and IB in the driver 5. As shown in FIG. 13, at respective periodic rising edges of the internal synchronization clock ICK, the respective internal image data IR, IG, and IB are sequentially transmitted.
According to the conventional method in which a transmission line is provided per bit of image data, in an exemplary case where image data for respective one of red (R), green (G), and blue (B) is represented by 3 bits, only nine transmission lines are required in total. However, in the above-described case where image data for respective one of red (R), green (G), and blue (B) is represented by 8 bits, 24 data lines are required in total. That is, the number of lines is increased by 15 as compared with the case of 3-bit image data. The data lines are connected to the driver 5, for example, through the driver substrate 4, and the width of the substrate 4 is desired to be as small as possible. The reason is described below. The driver substrates 4 are connected on both sides of the display device 2. If each substrate has a large width, the size of the resultant module is considerably large. As a matter of fact, the number of transmission lines is required to be as small as possible. The increase in number of data lines of the transmission line set 8 by 15 as in the case of 8-bit image data may be a critical problem for some purposes of the module. For example, in the case of the note-type electronic computer, the size is critical.
As for the driver itself, the increase in number of data lines by 15 as compared with the case of 3-bit image data results in a considerable increase in number of input terminals. Thus, the pitch of the input terminals is extremely small, which causes a difficulty of installation.
Table 1 below shows an example of the number and the pitch of input terminals of an actual driver for 3-bit image data which is installed in a film-like package (i.e., a so-called tape carrier package). The width of the driver is determined by the size of the display device, so that the width of the driver cannot be increased even if the driver is designed for 8-bit image data. Table 2 below shows an example of the number and the pitch of input terminals of an actual driver for 8-bit image data which is installed in a package having the same size as that in the 3-bit case. Herein, when the driver is designed for 8-bit data, the number of gray-scale power supplies is 9, and the numbers of other signals are the same as those in the 3-bit case.
TABLE 1 ______________________________________ Clock 1 Data input 9 Gray-scale power supply 8 Driving power supply 4 Control signal, etc. 9 Total number of input-side terminals 31 Pitch of input-side terminals 0.80 mm ______________________________________
TABLE 2 ______________________________________ Clock 1 Data input 24 Gray-scale power supply 9 Driving power supply 4 Control signal, etc. 9 Total number of input-side terminals 47 Pitch of input-side terminals 0.52 mm ______________________________________
As shown in the tables, in the case of the 8-bit data, the pitch of terminals is extremely reduced. In practice, this makes it difficult to perform automatic soldering by a machine for mass production. In addition, the width of each terminal is reduced, so that the mechanical strength is also reduced. Because of these facts, such devices are difficult to be commercially available, and the production cost thereof is significantly increased. Moreover, the size of the driver substrate is inevitably increased, so that the module using a driver for 8-bit data cannot be realized in the same size as that of the module using a driver for 3-bit data. This adversely affects the quality of the product.